This invention relates to functional testing and debugging of integrated circuits (ICs), and in particular testing and debugging of systems-on-chip (SoCs) that include blocks of previously verified logic, referred to as cores.
Determining the value of an internal signal in an IC is a fundamental problem in debugging a malfunctioning circuit when one is trying to find the root cause of its misbehavior. Of course, this problem is relevant only for signals that are not part of the circuit's state, because the values of signals that are part of the circuit's state can be easily determined by scanning out the state registers. That's because in modern ICs, all registers can be configured as shift registers, whose contents can be set by a scan-in operation, and can be read by a scan-out operation.
A useful technique for checking the design of ICs is called assertion checking. In assertion checking, a collection of conditions is identified that are expected to hold true at any time during the operation of a properly working SoC. The model of the SoC being tested can be simulated by application of various input test vectors, and its signals can be then checked against the collection of assertions. In a simulation, the signals checked by an assertion may include any internal signal. When an assertion “fires,” indicating that the asserted condition that should be met is not met, simulation can stop and the party performing the testing can attempt to analyze the reason for the assertion's failure.
The aforementioned U.S. patent application Ser. No. 10/425,101 discloses an SoC arrangement where cores of the SoC are encompassed by wrappers, and at least some of the wrappers include a functionally reconfigurable module (FRM). The aforementioned U.S. patent application Ser. No. 10/956,854 discloses use of the FRM in efficient assertion checking of SoCs.
Assertion checking in hardware, in contrast to simulation, is limited to checking only those signals that are made visible to the checking hardware. The set of signals to be checked at run-time is defined during the design of the SoC, and different subsets of this set can be selected at run-time. Such an example can be found in the paper “Silicon Debug: Scan Chains Alone Are Not Enough” by Rootselaar and Vermeulen, Proceedings of the International Test Conference, 1999
If assertion checking is done when the functional clocks of the SoC have stopped, then the values stored in flip-flops of the SoC (and thus form a part of—or in part define—the state of the SoC) can be also examined by full-scan dumps. A full-scan dump consists of scanning out all the flip-flop values and then using software to extract the values needed to be examined. A different analysis method is described in the aforementioned Ser. No. 11/051,774, where bit extractors are configured in FRMs to extract the bits required for the assertion checking and make them available to assertion checkers that are also implemented in FRMs. The converse of bit extractors are bit injectors where flip-flops of the SoC are set via a stream of scanned-in bits.
One limitation common to all the methods mentioned above is that values of outputs of combinatorial logic elements within the SoC which are not directly observable by the checking hardware cannot be used for assertion checking. The need to determine the value of such a signal may appear many times during the hardware debugging process, and currently there is no method to determine such a value in a malfunctioning circuit. It is an objective, therefore, to enable checking the signal value of any internal point of an SoC in the course of debugging an SoC.